From 3cc2c38d50741fffb9193851a4a3b7c636f7cd4d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:38:23 +0200 Subject: soc/intel/broadwell: Separate PCH in devicetree Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/purism/librem_bdw/variants/librem13v1') diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 237e6979ec..256077cbd9 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" @@ -11,6 +11,6 @@ chip soc/intel/broadwell register "sata_port3_gen3_dtle" = "9" device pci 1c.2 on end # PCIe Port #3 - LAN -# end + end end end -- cgit v1.2.3