From dcddc53fde2d559beef998d3c17e9b7a227e3665 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 03:39:24 +0200 Subject: skl mainboards/dt: Move genx_dec settings into LPC device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner Reviewed-by: Jonathon Hall Reviewed-by: Erik van den Bogaert Reviewed-by: Eric Lai Reviewed-by: Marvin Evers Tested-by: build bot (Jenkins) --- src/mainboard/protectli/vault_kbl/devicetree.cb | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src/mainboard/protectli') diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 61481960e5..0b5d0cd4a2 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,11 +12,6 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x007c0a01" - register "gen3_dec" = "0x000c03e1" - register "gen4_dec" = "0x001c02e1" - register "eist_enable" = "1" # Disable DPTF @@ -202,6 +197,10 @@ chip soc/intel/skylake "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" end device ref lpc_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" chip superio/ite/it8772f register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" -- cgit v1.2.3