From 69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 13:52:11 +0100 Subject: mb/*: Remove lapic from devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/protectli/vault_bsw/devicetree.cb | 4 +--- src/mainboard/protectli/vault_kbl/devicetree.cb | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'src/mainboard/protectli') diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb index 4b750c00f0..02a1642092 100644 --- a/src/mainboard/protectli/vault_bsw/devicetree.cb +++ b/src/mainboard/protectli/vault_bsw/devicetree.cb @@ -79,9 +79,7 @@ chip soc/intel/braswell # Enable SERIRQ continuous register "serirq_mode" = "SERIRQ_CONTINUOUS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping GFX diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index feb8b9f1e3..4e4cbac04a 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -189,9 +189,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3