From 83565dea8638841e522b64e74a4240002bba789d Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Wed, 27 Mar 2019 11:35:48 +0100 Subject: mb/protectli/vault: Add FW2B and FW4B Braswell based boards support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Frans Hendriks --- src/mainboard/protectli/vault_bsw/onboard.h | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 src/mainboard/protectli/vault_bsw/onboard.h (limited to 'src/mainboard/protectli/vault_bsw/onboard.h') diff --git a/src/mainboard/protectli/vault_bsw/onboard.h b/src/mainboard/protectli/vault_bsw/onboard.h new file mode 100644 index 0000000000..fcdb3a70b8 --- /dev/null +++ b/src/mainboard/protectli/vault_bsw/onboard.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + + +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 77 + +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 + +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5670" +#define AUDIO_CODEC_CID "10EC5670" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1C + +#define BCRD2_PMIC_I2C_BUS 0x01 + +#endif -- cgit v1.2.3