From 0d18da8627289ff2c7ca14866878274a41aa959d Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Mon, 21 Dec 2020 03:46:58 +0100 Subject: mb/prodrive/hermes: do UART pad configuration at board-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Change-Id: I5b99a66fb64683f3647ebff3ab01ceb52058f79c Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/prodrive/hermes/variants/baseboard/gpio.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/mainboard/prodrive/hermes/variants/baseboard/gpio.c') diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c index 096dc35785..c95e9d2301 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c @@ -389,6 +389,18 @@ const struct pad_config early_gpio_table[] = { /* LED */ PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */ + + /* UART0 */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ + + /* UART1 */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ + + /* UART2 */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ }; void program_gpio_pads(void) -- cgit v1.2.3