From b646e28769f27ee2812925f63fe2f73c67e23c9e Mon Sep 17 00:00:00 2001
From: Christian Walter <christian.walter@9elements.com>
Date: Thu, 9 Jan 2020 15:42:42 +0100
Subject: mb/prodrive/hermes: Add new mainboard port

This patch adds support for the Prodrive Hermes mainboard.

Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41.

Untested:
* CNVi
* Intel Graphics

Tested:
* CPU Intel Xeon E2288G
* CPU Intel Core i3-9100F
* CPU Intel Core i7 9700KF
* CPU Intel Core i7 9700E
* CPU Intel Core i7 9700F
* CPU Intel Core i5 9600K
* CPU Intel Pentium Gold G5400
* PCIe Link Width x8 on Slot6 by changing PCIe mux
* All four DDR4 slots in different configurations
* USB2.0 HDR1
* USB2.0 HDR2
* USB3.0 HDR
* Slot1
* Slot2
* Slot3
* Slot4
* Slot6
* M2.M NVMEe
* Ethernet PHYs 0-4
* Aspeed BMC PCIe
* Aspeed BMC USB
* Aspeed Graphics init
* USB3 backplane all working
* I801 SMBUS

Not Working:
* Intel HDA

Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
 src/mainboard/prodrive/hermes/memory.c | 44 ++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 src/mainboard/prodrive/hermes/memory.c

(limited to 'src/mainboard/prodrive/hermes/memory.c')

diff --git a/src/mainboard/prodrive/hermes/memory.c b/src/mainboard/prodrive/hermes/memory.c
new file mode 100644
index 0000000000..0ff21c4754
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/memory.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variant/variants.h>
+#include <soc/cnl_memcfg_init.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg_cfg = {
+	/* Access memory info through SMBUS. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA0}
+	},
+	.spd[1] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA2}
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA4}
+	},
+	.spd[3] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA6}
+	},
+
+	/* Baseboard uses 121, 81 and 100 rcomp resistors */
+	.rcomp_resistor = {121, 81, 100},
+
+	/* Baseboard Rcomp target values. */
+	.rcomp_targets = {100, 40, 20, 20, 26},
+
+	/* Baseboard is an interleaved design */
+	.dq_pins_interleaved = 1,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Disable Early Command Training */
+	.ect = 0,
+};
+
+const struct cnl_mb_cfg *variant_memcfg_config(void)
+{
+	return &baseboard_memcfg_cfg;
+}
-- 
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