From 119ace0908b66b718c4b581423309648b10e4bf7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 2 Oct 2019 16:02:06 +0200 Subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/prodrive/hermes/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/prodrive/hermes/devicetree.cb') diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index a89ba1b755..cae3d4c070 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -35,6 +35,7 @@ chip soc/intel/cannonlake device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2500 VGA end + register "PcieRpSlotImplemented[14]" = "1" end device pci 1f.0 on # LPC Interface chip drivers/pc80/tpm -- cgit v1.2.3