From 12440ce63e3f96b32311f4ebde4ef0861dbcec02 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 23 Oct 2019 11:30:22 +0200 Subject: drivers/intel/fsp1_1: Fake microcode update to make FSP happy The FSP loops through microcode updates and at the end checks if the microcode revision is not zero. Since we update the microcode before loading FSP, this is the case and a fake microcode can be passed to the FSP. The advantage is that the Kconfig symbols to specify the location and the size of the microcode blob can be dropped. Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/portwell/m107/Kconfig | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/mainboard/portwell/m107/Kconfig') diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index 3ab20f0b77..e5e3ff590a 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -61,16 +61,6 @@ config CBFS_SIZE hex default 0x00800000 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x10C00 - help - This should be updated when the microcode patch changes. - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xFFFE9400 - config MRC_SETTINGS_CACHE_SIZE hex default 0x08000 -- cgit v1.2.3