From c85cce077cc9ded8f33b9b059ce0b165da618639 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Tue, 3 Nov 2020 00:29:39 +0100
Subject: mb/**/cmos.layout: Indent everything with tabs

Time has shown that using spaces never converges into proper alignment.

Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
---
 src/mainboard/pcengines/apu1/cmos.layout | 38 ++++++++--------
 src/mainboard/pcengines/apu2/cmos.layout | 78 ++++++++++++++++----------------
 2 files changed, 58 insertions(+), 58 deletions(-)

(limited to 'src/mainboard/pcengines')

diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
index a1165b118b..dd3cd91f30 100644
--- a/src/mainboard/pcengines/apu1/cmos.layout
+++ b/src/mainboard/pcengines/apu1/cmos.layout
@@ -1,34 +1,34 @@
 entries
 
 # <start-bit> <bit-length> <config> <config-id> <parameter-name>
-0             384          r        0           reserved_memory
-384           4            r        0           reboot_bits
+0	384	r	0	reserved_memory
+384	4	r	0	reboot_bits
 # leave 3 bits to make checksummed area start byte-aligned
-392           1            e        2           boot_option
-393           1            e        1           multi_core
-400           4            e        4           debug_level
+392	1	e	2	boot_option
+393	1	e	1	multi_core
+400	4	e	4	debug_level
 # leave 7 bits to make checksummed area end byte-aligned
-408           16           h        0           check_sum
+408	16	h	0	check_sum
 
 enumerations
 
 #<config-id>  <value>  <label>
 ## for multi_core
-1             0        Enable
-1             1        Disable
+1	0	Enable
+1	1	Disable
 ## for boot_option
-2             0        Fallback
-2             1        Normal
+2	0	Fallback
+2	1	Normal
 ## for debug_level
-4             0        Emerg
-4             1        Alert
-4             2        Crit
-4             3        Err
-4             4        Warning
-4             5        Notice
-4             6        Info
-4             7        Debug
-4             8        Spew
+4	0	Emerg
+4	1	Alert
+4	2	Crit
+4	3	Err
+4	4	Warning
+4	5	Notice
+4	6	Info
+4	7	Debug
+4	8	Spew
 
 checksums
 
diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout
index dd35365409..586e22a9bf 100644
--- a/src/mainboard/pcengines/apu2/cmos.layout
+++ b/src/mainboard/pcengines/apu2/cmos.layout
@@ -5,49 +5,49 @@
 
 entries
 
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       r       0        reboot_bits
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
+0	384	r	0	reserved_memory
+384	1	e	4	boot_option
+388	4	r	0	reboot_bits
+395	1	e	1	hw_scrubber
+396	1	e	1	interleave_chip_selects
+397	2	e	8	max_mem_clock
+399	1	e	2	multi_core
+400	1	e	1	power_on_after_fail
+412	4	e	6	debug_level
+440	4	e	9	slow_cpu
+444	1	e	1	nmi
+445	1	e	1	iommu
+456	1	e	1	ECC_memory
+728	256	h	0	user_data
+984	16	h	0	check_sum
 # Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
+1000	24	r	0	amd_reserved
 
 enumerations
 
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
+#ID	value	text
+1	0	Disable
+1	1	Enable
+2	0	Enable
+2	1	Disable
+4	0	Fallback
+4	1	Normal
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+8	0	400Mhz
+8	1	333Mhz
+8	2	266Mhz
+8	3	200Mhz
+9	0	off
+9	1	87.5%
+9	2	75.0%
+9	3	62.5%
+9	4	50.0%
+9	5	37.5%
+9	6	25.0%
+9	7	12.5%
 
 checksums
 
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