From 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 20 Nov 2010 10:31:00 +0000 Subject: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/pcengines/alix1c/romstage.c | 4 +--- src/mainboard/pcengines/alix2d/romstage.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'src/mainboard/pcengines') diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f0c4ed6325..4b7d0fde04 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -32,6 +32,7 @@ #include #include #include "southbridge/amd/cs5536/cs5536.h" +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -106,9 +107,6 @@ static u8 spd_read_byte(u8 device, u8 address) #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xa0 -#define DIMM1 0xa2 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 10ab27d662..44e14ac7ec 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -32,6 +32,7 @@ #include #include #include "southbridge/amd/cs5536/cs5536.h" +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -105,9 +106,6 @@ static u8 spd_read_byte(u8 device, u8 address) #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xa0 -#define DIMM1 0xa2 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" -- cgit v1.2.3