From 65f05505a6b7e9e1e9b45c9f6aae34fccd7a7f32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 12 Feb 2020 13:10:23 +0100 Subject: superio/nuvoton/nct5104d: add chip config option to reset GPIOs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define a chip option to explicitly soft reset all enabled GPIOs to default state. TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration using nctgpio module and check whether GPIOs are reset after reboot Signed-off-by: Michał Żygowski Change-Id: Iae4205574800138402cbc95f4948167265a80d15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38850 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/pcengines/apu1/devicetree.cb | 1 + src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb | 1 + src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 1 + src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb | 1 + 4 files changed, 4 insertions(+) (limited to 'src/mainboard/pcengines') diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 4974cfbfbb..dd851a7133 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -41,6 +41,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 3528e86362..672155b049 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 13643a42c0..d743da6b66 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index f5082d466f..c08e5b24e2 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -44,6 +44,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 -- cgit v1.2.3