From 03a3404d5b9c198c4ac74eb076df108149534b19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 31 Mar 2020 13:36:23 +0200 Subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway. Signed-off-by: Michał Żygowski Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/pcengines/apu2/OemCustomize.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mainboard/pcengines/apu2') diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index e47a2c8317..8b6cd038e8 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -35,7 +35,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_PORT3_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -47,7 +47,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -59,7 +59,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_NIC_RESET_ID, - ClkPmSupportEnabled) + 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -83,7 +83,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, PCIE_GFX_RESET_ID, - ClkPmSupportEnabled) + 0) } }; -- cgit v1.2.3