From 302951d9c3eb812a42cb6560a5d2b0096fbe85d5 Mon Sep 17 00:00:00 2001 From: Piotr Kleinschmidt Date: Wed, 8 Jan 2020 16:09:59 +0100 Subject: mb/pcengines/*: enable simple IO-based GPIO control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Nuvoton NCT5104D GPIO IO VLDN and define an IO base address unused by any peripheral for GPIO use. Signed-off-by: Piotr Kleinschmidt Signed-off-by: Michał Żygowski Change-Id: I034c5d0169b8d97eac97a20c92c22816fd674f79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38275 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard/pcengines/apu2/variants/apu3') diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index ad299657f1..524f30f3d8 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -64,7 +64,10 @@ chip northbridge/amd/pi/00730F01/root_complex io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.8 off end + device pnp 2e.008 off end + device pnp 2e.108 on + io 0x60 = 0x220 + end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end device pnp 2e.107 on end -- cgit v1.2.3