From c27df8787801dac421b98c4dbb447e519065ae95 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 16 Jan 2017 19:58:53 +0200 Subject: pcengines/apu2: Refactor reading memory strap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/pcengines/apu2/gpio_ftns.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/mainboard/pcengines/apu2/gpio_ftns.c') diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index fd1fb3c9e2..12b8f9464b 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -16,6 +16,7 @@ #include #include #include +#include "FchPlatform.h" #include "gpio_ftns.h" void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) @@ -32,3 +33,16 @@ void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, bdata |= setting; /* set direction and data value */ *memptr = bdata; } + +int get_spd_offset(void) +{ + u8 index = 0; + /* One SPD file contains all 4 options, determine which index to + * read here, then call into the standard routines. + */ + u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE); + if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0; + if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1; + + return index; +} -- cgit v1.2.3