From dcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Fri, 27 May 2016 12:04:13 +0200 Subject: pcengines/apu2: add board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król Signed-off-by: Philipp Deppenwiese Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/pcengines/apu2/dsdt.asl | 84 +++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 src/mainboard/pcengines/apu2/dsdt.asl (limited to 'src/mainboard/pcengines/apu2/dsdt.asl') diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl new file mode 100644 index 0000000000..1fcd9054b4 --- /dev/null +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Contains the supported sleep states for this chipset */ + #include + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ -- cgit v1.2.3