From 8e23270405b4ecd27abb02af9cc8a985aa01edcf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 29 Apr 2021 17:53:10 +0200 Subject: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bank interleaving does not work on this platform, disable it. Additionally enable ECC feature on SKUs supporting it. AmdIntPost returns success thanks to these settings. TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after AmdInitPost Signed-off-by: Michał Żygowski Change-Id: I010645f53b404341895d0545855905e81c89165e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/pcengines/apu2/OemCustomize.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/mainboard/pcengines/apu2/OemCustomize.c') diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6e6b5a273a..95af6ef92d 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -3,6 +3,8 @@ #include #include +#include "gpio_ftns.h" + static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -78,3 +80,17 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CpbMode = CpbModeAuto; } + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* + * Bank interleaving does not work on this platform. + * Disable it so AGESA will return success. + */ + Post->MemConfig.EnableBankIntlv = FALSE; + /* 4GB variants have ECC */ + if (get_spd_offset()) + Post->MemConfig.EnableEccFeature = TRUE; + else + Post->MemConfig.EnableEccFeature = FALSE; +} -- cgit v1.2.3