From e1c36aecd8c5ad580595da58e180b06195df5f00 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 13 Oct 2015 15:01:15 +0300 Subject: pcengines/apu1: Add RS485 configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/14998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/mainboard/pcengines/apu1/mainboard.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'src/mainboard/pcengines/apu1/mainboard.c') diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 96b20209f9..055cd58dd5 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -158,6 +158,28 @@ static void config_gpio_mux(void) gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; } +static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) +{ + struct resource *res; + res = new_resource(dev, reg); + res->base = val; + res->size = 0; + res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; +} + +static void config_addon_uart(void) +{ + struct device *uart; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + if (uart && uart->enabled && CONFIG_UART_C_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + if (uart && uart->enabled && CONFIG_UART_D_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); +} + /** * TODO * SB CIMx callback @@ -182,6 +204,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); + config_addon_uart(); /* Power off unused clock pins of GPP PCIe devices */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); -- cgit v1.2.3