From df95b51ab636f78f66c27d7a7b0aebf245f288c1 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 6 Nov 2015 18:32:43 +0100 Subject: pcengines/apu1: enable use of clkreq pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit only enable pcie gpp clocks when the corresponding clkreq pin is asserted Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2 Signed-off-by: Felix Held Reviewed-on: http://review.coreboot.org/12353 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Kyösti Mälkki --- src/mainboard/pcengines/apu1/mainboard.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/pcengines/apu1/mainboard.c') diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 82cf9921a5..f91e8799d8 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -187,10 +187,10 @@ static void mainboard_enable(device_t dev) u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); /* GPP CLK0-2 are connected to the 3 ethernet chips * GPP CLK3-4 are connected to the miniPCIe slots */ - write8(misc_mem_clk_cntrl + 0, 0xFF); - write8(misc_mem_clk_cntrl + 1, 0xFF); + write8(misc_mem_clk_cntrl + 0, 0x21); + write8(misc_mem_clk_cntrl + 1, 0x43); /* GPP CLK5 is only connected to test pads -> disable */ - write8(misc_mem_clk_cntrl + 2, 0x0F); + write8(misc_mem_clk_cntrl + 2, 0x05); /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ write8(misc_mem_clk_cntrl + 3, 0x00); write8(misc_mem_clk_cntrl + 4, 0x00); -- cgit v1.2.3