From b06015b92ec0a44646d18ec32f2cb333e965e616 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 6 Nov 2015 18:31:01 +0100 Subject: pcengines/apu1: disable unused clock outputs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit disable unconnected FCH clock outputs to save some power Change-Id: Ib3efebb8656392d58d762c23827168017d273de8 Signed-off-by: Felix Held Reviewed-on: http://review.coreboot.org/12082 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Kyösti Mälkki --- src/mainboard/pcengines/apu1/mainboard.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/mainboard/pcengines/apu1/mainboard.c') diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index f80f24ec87..82cf9921a5 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -183,6 +183,18 @@ static void mainboard_enable(device_t dev) config_gpio_mux(); + /* Power off unused clock pins of GPP PCIe devices */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + /* GPP CLK0-2 are connected to the 3 ethernet chips + * GPP CLK3-4 are connected to the miniPCIe slots */ + write8(misc_mem_clk_cntrl + 0, 0xFF); + write8(misc_mem_clk_cntrl + 1, 0xFF); + /* GPP CLK5 is only connected to test pads -> disable */ + write8(misc_mem_clk_cntrl + 2, 0x0F); + /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ + write8(misc_mem_clk_cntrl + 3, 0x00); + write8(misc_mem_clk_cntrl + 4, 0x00); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } -- cgit v1.2.3