From 08fc8fff255c3aa27362655887a5f5bcd786857c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Aug 2018 12:19:10 +0200 Subject: src/mainboard: Fix typo Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/pcengines/apu1/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/pcengines/apu1/mainboard.c') diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 290a0ed231..de949371fa 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -91,7 +91,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { */ /* * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because of PCI INT_PIN swizzle isnt implemented to match + * but because of PCI INT_PIN swizzle isn't implemented to match * the IDSEL (dev 3) of the slot, the table is adjusted for the * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. -- cgit v1.2.3