From 780935687d74f89a25a9c58952314be6af61c348 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 11 Nov 2014 17:22:23 +0200 Subject: pcengines/apu1: Implement board GPIOs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some GPIO pins are shared with (disabled) PCI bridge 0:14.4. As our PCI subsystem currently does not configure PCI bridges that are marked disabled, but remain visible in the hardware, we cannot mark 0:14.4 disabled in devicetree just yet. Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8326 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/mainboard/pcengines/apu1/gpio_ftns.c | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 src/mainboard/pcengines/apu1/gpio_ftns.c (limited to 'src/mainboard/pcengines/apu1/gpio_ftns.c') diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c new file mode 100644 index 0000000000..b683543240 --- /dev/null +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "SBPLATFORM.h" +#include +#include "gpio_ftns.h" + +u32 find_gpio_base(void) +{ + u8 pm_index, pm_data; + u32 base_addr = 0; + + /* Find the ACPImmioAddr base address */ + for ( pm_index = 0x27; pm_index > 0x23; pm_index-- ) { + outb( pm_index, PM_INDEX ); + pm_data = inb( PM_DATA ); + base_addr <<= 8; + base_addr |= (u32)pm_data; + } + base_addr &= 0xFFFFF000; + return (base_addr); +} + +void configure_gpio(u32 base_addr, u32 gpio, u8 iomux_ftn, u8 setting) +{ + u8 bdata; + u8 *memptr; + + memptr = (u8 *)(base_addr + IOMUX_OFFSET + gpio); + *memptr = iomux_ftn; + + memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio); + bdata = *memptr; + bdata &= 0x07; + bdata |= setting; /* set direction and data value */ + *memptr = bdata; +} + +u8 read_gpio(u32 base_addr, u32 gpio) +{ + u8 *memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio); + return (*memptr & GPIO_DATA_IN) ? 1 : 0; +} + +int get_spd_offset(void) +{ + u32 base_addr = find_gpio_base(); + u8 spd_offset = read_gpio(base_addr, GPIO_16); + return spd_offset; +} -- cgit v1.2.3