From f09e6d47b8174017d8964780b916dec9dd0b2009 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sat, 10 Jan 2015 12:13:23 +0200
Subject: pcengines/apu1: Fork of amd/persimmon
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Drop persimmon customization for superio, azalia, PCI-e reset etc.

Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8324
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
 src/mainboard/pcengines/apu1/dsdt.asl | 69 +++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 src/mainboard/pcengines/apu1/dsdt.asl

(limited to 'src/mainboard/pcengines/apu1/dsdt.asl')

diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl
new file mode 100644
index 0000000000..25520b2368
--- /dev/null
+++ b/src/mainboard/pcengines/apu1/dsdt.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",	/* Output filename */
+	"DSDT",		/* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"AMD   ",	/* OEMID */
+	"COREBOOT",	/* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
+
+	#include "acpi/mainboard.asl"
+
+	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+		/* global utility methods expected within the \_SB scope */
+		#include <arch/x86/acpi/globutil.asl>
+
+		Device(PCI0) {
+
+			/* Describe the AMD Northbridge */
+			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
+
+			/* Describe the AMD Fusion Controller Hub Southbridge */
+			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+		}
+	}   /* End Scope(_SB)  */
+
+	/* Contains the supported sleep states for this chipset */
+	#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
+
+	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+	#include "acpi/sleep.asl"
+
+	#include "acpi/gpe.asl"
+	#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
+	#include "acpi/thermal.asl"
+}
+/* End of ASL file */
-- 
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