From 8c678cf46a2bc9716a84609615b602422a233a9e Mon Sep 17 00:00:00 2001 From: Philipp Deppenwiese Date: Fri, 10 Aug 2018 16:15:14 -0700 Subject: mainboard/opencellular/elgon: Add mainboard support Tested on Elgon EVT board and boots into GNU/Linux. TODO: * Add hard reset function for VBOOT. * Add EC code * Add SPI flash write protection Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Signed-off-by: Philipp Deppenwiese Reviewed-on: https://review.coreboot.org/28024 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/mainboard/opencellular/elgon/bootblock.c | 56 ++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 src/mainboard/opencellular/elgon/bootblock.c (limited to 'src/mainboard/opencellular/elgon/bootblock.c') diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c new file mode 100644 index 0000000000..e6109f1072 --- /dev/null +++ b/src/mainboard/opencellular/elgon/bootblock.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "mainboard.h" + +void bootblock_mainboard_early_init(void) +{ + /* Route UART0 to CON1 */ + gpio_output(ELGON_GPIO_UART_SEL, 0); + + /* Turn off error LED */ + gpio_output(ELGON_GPIO_ERROR_LED, 0); + + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE)) + uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD); + } +} + +static void configure_spi_flash(void) +{ + /* The maximum SPI frequency for error free transmission is at 30 Mhz */ + spi_init_custom(0, // bus + 28000000, // speed Hz + 0, // idle low disabled + 0, // zero idle cycles between transfers + 0, // MSB first + 0, // Chip select 0 + 1); // assert is high + + /* Route SPI to SoC */ + gpio_output(ELGON_GPIO_SPI_MUX, 1); +} + +void bootblock_mainboard_init(void) +{ + configure_spi_flash(); + // FIXME: Check SPI flash WP bits +} -- cgit v1.2.3