From 3acea5c51abd09bb578cfb35952b9dbd96be21fe Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Fri, 8 Jan 2021 15:24:25 +0800 Subject: ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocp 1. These are common OCP/Facebook IPMI OEM commands, move from mainboard into drivers/ipmi/ocp to avoid code duplication and provide better reusability. 2. OCP Tioga Pass enables IPMI_OCP driver. Tested=On OCP Delta Lake and Tioga Pass verify the commands still work correctly. Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marc Jones --- src/mainboard/ocp/tiogapass/Kconfig | 1 + src/mainboard/ocp/tiogapass/devicetree.cb | 3 +++ src/mainboard/ocp/tiogapass/ipmi.c | 18 +----------------- src/mainboard/ocp/tiogapass/ipmi.h | 12 ------------ src/mainboard/ocp/tiogapass/ramstage.c | 10 ---------- src/mainboard/ocp/tiogapass/romstage.c | 5 ++++- 6 files changed, 9 insertions(+), 40 deletions(-) (limited to 'src/mainboard/ocp/tiogapass') diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 67c1fa9d52..2ead76db72 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select IPMI_KCS select IPMI_KCS_ROMSTAGE + select IPMI_OCP select MAINBOARD_USES_FSP2_0 select OCP_DMI select PARALLEL_MP_AP_WORK diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 488f677a95..833bb20e21 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -76,6 +76,9 @@ chip soc/intel/xeon_sp/skx register "bmc_i2c_address" = "0x20" register "bmc_boot_timeout" = "90" end + chip drivers/ipmi/ocp # OCP specific IPMI porting + device pnp ca2.1 on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c index 0cdf110bd8..74f96fe36c 100644 --- a/src/mainboard/ocp/tiogapass/ipmi.c +++ b/src/mainboard/ocp/tiogapass/ipmi.c @@ -3,29 +3,13 @@ #include #include #include +#include #include #include #include "ipmi.h" #include "vpd.h" -void ipmi_set_ppin(struct ppin_req *req) -{ - int ret; - struct ipmi_rsp rsp; - - ret = ipmi_kcs_message(CONFIG_BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, - (const unsigned char *) req, sizeof(*req), - (unsigned char *) &rsp, sizeof(rsp)); - - if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { - printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", - __func__, ret, rsp.completion_code); - return; - } - printk(BIOS_DEBUG, "IPMI Set PPIN to BMC done.\n"); -} - void init_frb2_wdt(void) { char val[VPD_LEN]; diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h index 798f3125ef..93101c2bfe 100644 --- a/src/mainboard/ocp/tiogapass/ipmi.h +++ b/src/mainboard/ocp/tiogapass/ipmi.h @@ -4,17 +4,5 @@ #define TIOGAPASS_IPMI_H #include -#define IPMI_NETFN_OEM 0x30 -#define IPMI_OEM_SET_PPIN 0x77 - -/* PPIN for 2 CPU IPMI request */ -struct ppin_req { - uint32_t cpu0_lo; - uint32_t cpu0_hi; - uint32_t cpu1_lo; - uint32_t cpu1_hi; -} __packed; -/* Send CPU0 and CPU1 PPIN to BMC */ -void ipmi_set_ppin(struct ppin_req *req); void init_frb2_wdt(void); #endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index 29148d14ec..df7720538e 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -7,8 +7,6 @@ #include #include -#include "ipmi.h" - extern struct fru_info_str fru_strings; static const struct port_information SMBIOS_type8_info[] = { @@ -185,14 +183,6 @@ static void mainboard_enable(struct device *dev) static void mainboard_final(void *chip_info) { - struct ppin_req req; - - req.cpu0_lo = xeon_sp_ppin[0].lo; - req.cpu0_hi = xeon_sp_ppin[0].hi; - req.cpu1_lo = xeon_sp_ppin[1].lo; - req.cpu1_hi = xeon_sp_ppin[1].hi; - /* Set PPIN to BMC */ - ipmi_set_ppin(&req); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index fb2ce0217a..20c74660ce 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -53,8 +54,10 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { /* It's better to run get BMC selftest result first */ - if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { + ipmi_set_post_start(CONFIG_BMC_KCS_BASE); init_frb2_wdt(); + } mainboard_config_iio(mupd); /* do not configure GPIO controller inside FSP-M */ -- cgit v1.2.3