From 662da6cf7b181ea2787ba001d9cbb6d41916abec Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 16 Mar 2020 22:46:57 -0700 Subject: soc/intel/xeon_sp: Refactor code to allow for additional CPUs types Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) --- src/mainboard/ocp/tiogapass/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/ocp/tiogapass/devicetree.cb') diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index c2eddf270c..51e6a62eb1 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -chip soc/intel/xeon_sp +chip soc/intel/xeon_sp/skx register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" -- cgit v1.2.3