From 8541325f38c754299664b9f9320a29ee8394bb04 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Wed, 21 Jul 2021 12:17:53 +0800 Subject: mb/ocp/deltalake: Revert OVERRIDE_UART_FOR_CONSOLE This reverts commit f6efeae66c (mb/ocp/deltalake: Override uart base address via VPD variable). Both SOL and UART would use 0x2f8, disabling it can also avoid searching flash VPD during each UART tx. Change-Id: I453fdddbb883eb956bac708913c17bb581f75b9d Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/56468 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang Reviewed-by: Angel Pons --- src/mainboard/ocp/deltalake/vpd.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/ocp/deltalake/vpd.h') diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index fb33ef26f5..f9271343a3 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -37,10 +37,6 @@ #define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" #define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 -/* coreboot uart io select: 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8 */ -#define COREBOOT_UART_IO "coreboot_uart_io" -#define COREBOOT_UART_IO_DEFAULT 1 - /* FSP dimm frequency limit, 0:Auto, 1:DDR_1333, 2:DDR_1600, 3:DDR_1866, 4:DDR_2133, * 5:DDR_2400, 6:DDR_2666, 7:DDR_2933, 8:DDR_3200 */ #define FSP_DIMM_FREQ "fsp_dimm_freq" -- cgit v1.2.3