From dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Thu, 21 Oct 2004 10:44:08 +0000 Subject: - Bump the LinuxBIOS major version - Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/newisys/khepri/Config.lb | 142 +++++++++++++++++-------------- src/mainboard/newisys/khepri/chip.h | 2 +- src/mainboard/newisys/khepri/mainboard.c | 28 +----- 3 files changed, 79 insertions(+), 93 deletions(-) (limited to 'src/mainboard/newisys') diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb index c96cfc7240..81b943c285 100644 --- a/src/mainboard/newisys/khepri/Config.lb +++ b/src/mainboard/newisys/khepri/Config.lb @@ -253,75 +253,87 @@ mainboardinit cpu/k8/disable_mmx_sse.inc dir /pc80 config chip.h -northbridge amd/amdk8 "mc0" - pci 0:18.0 - pci 0:18.0 - pci 0:18.0 - pci 0:18.1 - pci 0:18.2 - pci 0:18.3 - southbridge amd/amd8131 "amd8131" link 1 - pci 0:0.0 - pci 0:0.1 - pci 0:1.0 - pci 0:1.1 - end - southbridge amd/amd8111 "amd8111" link 1 - pci 0:0.0 - pci 0:1.0 on - pci 0:1.1 on - pci 0:1.2 on - pci 0:1.3 on - pci 0:1.5 on - pci 0:1.6 on - pci 1:0.0 on - pci 1:0.1 on - pci 1:0.2 on - pci 1:1.0 on - superio NSC/pc87360 link 1 - pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - pnp 2e.4 off # SWC - pnp 2e.5 off # Mouse - pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - pnp 2e.7 off # GPIO - pnp 2e.8 off # ACB - pnp 2e.9 off # FSCM - pnp 2e.a off # WDT +chip northbridge/amd/amdk8 + device pci_domain 0 on + device pci 18.0 on end # LDT 0 + device pci 18.0 on # LDT 1 + chip southbridge/amd/amd8131 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 on end + device pci 1.0 on end + end + device pci 1.0 on + chip superio/NSC/pc87360 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # ACB + device pnp 2e.9 off end # FSCM + device pnp 2e.a off end # WDT + + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on end + device pci 1.5 on end + device pci 1.6 on end + end + end # LDT1 + device pci 18.0 on end # LDT2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + + chip northbridge/amd/amdk8 + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end end end end -northbridge amd/amdk8 "mc1" - pci 0:19.0 - pci 0:19.0 - pci 0:19.0 - pci 0:19.1 - pci 0:19.2 - pci 0:19.3 -end - -cpu k8 "cpu0" - register "ldt1" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }" -end - -cpu k8 "cpu1" -end - ## ## Include the old serial code for those few places that still need it. ## diff --git a/src/mainboard/newisys/khepri/chip.h b/src/mainboard/newisys/khepri/chip.h index 7e8ef5210a..cb4a806d66 100644 --- a/src/mainboard/newisys/khepri/chip.h +++ b/src/mainboard/newisys/khepri/chip.h @@ -1,4 +1,4 @@ -extern struct chip_control mainboard_newisys_khepri_control; +extern struct chip_operations mainboard_newisys_khepri_control; struct mainboard_newisys_khepri_config { int nothing; diff --git a/src/mainboard/newisys/khepri/mainboard.c b/src/mainboard/newisys/khepri/mainboard.c index d170f48eb3..67ebd9add2 100644 --- a/src/mainboard/newisys/khepri/mainboard.c +++ b/src/mainboard/newisys/khepri/mainboard.c @@ -8,33 +8,7 @@ #include "../../../northbridge/amd/amdk8/northbridge.h" #include "chip.h" - -unsigned long initial_apicid[CONFIG_MAX_CPUS] = -{ - 0, 1, -}; - -static struct device_operations mainboard_operations = { - .read_resources = root_dev_read_resources, - .set_resources = root_dev_set_resources, - .enable_resources = enable_childrens_resources, - .init = 0, - .scan_bus = amdk8_scan_root_bus, - .enable = 0, -}; - -static void enumerate(struct chip *chip) -{ - struct chip *child; - dev_root.ops = &mainboard_operations; - chip->dev = &dev_root; - chip->bus = 0; - for(child = chip->children; child; child = child->next) { - child->bus = &dev_root.link[0]; - } -} -struct chip_control mainboard_newisys_khepri_control = { - .enumerate = enumerate, +struct chip_operations mainboard_newisys_khepri_control = { .name = "Newisys Khepri mainboard ", }; -- cgit v1.2.3