From f98a5d6a3207653e3e417162b4b7df4866417c92 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Feb 2018 09:32:17 +0100 Subject: mainboard/msi/ms9185: Fix coding style and remove commented code Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/23536 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/msi/ms9185/mptable.c | 61 +++++++++++++++++++------------------ src/mainboard/msi/ms9185/romstage.c | 29 ------------------ 2 files changed, 32 insertions(+), 58 deletions(-) (limited to 'src/mainboard/msi') diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index e93602be1c..1e517a3352 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) { device_t dev = 0; struct resource *res; - for(i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -72,17 +72,19 @@ static void *smp_write_config_table(void *v) //IDE outb(0x02, 0xc00); outb(0x0e, 0xc01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xf); //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i = 0; i < 3; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // - } + for (i = 0; i < 3; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // @@ -91,7 +93,7 @@ static void *smp_write_config_table(void *v) { device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { + if (dev) { uint32_t dword; dword = pci_read_config32(dev, 0x6c); dword |= (1 << 4); // enable interrupts @@ -101,46 +103,47 @@ static void *smp_write_config_table(void *v) //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 // AIC 8130 Galileo Technology... - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // - } + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // //pci slot (on bcm5785) - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); // - } + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); // //onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // - } + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // //onboard Broadcom - for(i = 0; i < 2; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // - } + for (i = 0; i < 2; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // // First PCI-E x8 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); // - } + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); // // Second PCI-E x8 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); // - } + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); // // Third PCI-E x1 - for(i = 0; i < 4; i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); // - } + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); // /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index a86b57a063..d8cff07ff3 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -106,18 +106,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_ms9185_resource_map(); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); - dump_pci_device(PCI_DEV(0, 0x19, 0)); -#endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); @@ -139,12 +133,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bcm5785_early_setup(); -#if 0 - //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); -#endif - #if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; @@ -179,27 +167,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 - int i; - for(i = 0; i < 2; i++) { - activate_spd_rom(sysinfo->ctrl+i); - dump_smbus_registers(); - } -#endif - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); -#if 0 - print_pci_devices(); -#endif - -#if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); - dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); -#endif } -- cgit v1.2.3