From f0a13ceb639f7a7d5a6e84a2c89f3deab0de757a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 8 Dec 2013 07:20:48 +0200 Subject: AMD boards: Fix includes for microcode updates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No ROMCC involved, no need to include .c files in romstage.c. Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/4501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel --- src/mainboard/msi/ms9652_fam10/romstage.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'src/mainboard/msi') diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 2571215b38..4fc723064c 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -72,11 +72,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/early_setup_ss.h" #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" -#include "cpu/amd/microcode/microcode.c" - -#if CONFIG_UPDATE_CPU_MICROCODE -#include "cpu/amd/model_10xxx/update_microcode.c" -#endif +#include "cpu/amd/microcode.h" #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -147,9 +143,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); -#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); -#endif + post_code(0x33); cpuSetAMDMSR(); -- cgit v1.2.3