From 83481eb0a30ab69b9b010801fc31812174d3d8bc Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sat, 31 Aug 2024 10:41:31 +0200 Subject: tree: use boolean for hybrid_storage_mode Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/msi/ms7d25/devicetree.cb | 2 +- src/mainboard/msi/ms7e06/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/msi') diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index e87467913f..d22cd92a18 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -82,7 +82,7 @@ chip soc/intel/alderlake [DDI_PORT_4] = DDI_ENABLE_HPD, }" - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" register "dmi_power_optimize_disable" = "1" # FIVR configuration diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 738c8a3030..298e9b01fe 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_VPGIO" register "pmc_gpe0_dw2" = "GPD" - register "hybrid_storage_mode" = "1" + register "hybrid_storage_mode" = "true" register "dmi_power_optimize_disable" = "1" # FIVR configuration -- cgit v1.2.3