From 78acf932912669eb0eb7f7280da1b3c550035ebb Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 18 Mar 2010 20:58:41 +0000 Subject: Remove remaining uses of HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/msi/ms7135/romstage.c | 6 ------ src/mainboard/msi/ms7260/Kconfig | 10 ---------- src/mainboard/msi/ms7260/romstage.c | 11 ----------- src/mainboard/msi/ms9282/Kconfig | 10 ---------- src/mainboard/msi/ms9652_fam10/Kconfig | 20 -------------------- src/mainboard/msi/ms9652_fam10/romstage.c | 10 ---------- 6 files changed, 67 deletions(-) (limited to 'src/mainboard/msi') diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 54753b2819..66a29b9fc6 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -47,8 +47,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#if CONFIG_USE_FAILOVER_IMAGE == 0 - /* Used by ck804_early_setup(). */ #define CK804_NUM 1 #define CK804_USE_NIC 1 @@ -98,8 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* CONFIG_USE_FAILOVER_IMAGE */ - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -121,7 +117,6 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); } -#if CONFIG_USE_FAILOVER_IMAGE == 0 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -204,4 +199,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif /* CONFIG_USE_FAILOVER_IMAGE */ diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index ce7a6b2734..52a3651c26 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM default n depends on BOARD_MSI_MS7260 -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_MSI_MS7260 - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_MSI_MS7260 - config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 6352841755..f2e654bb6d 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -58,8 +58,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE == 0 - #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -73,15 +71,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE == 0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -129,8 +123,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -152,8 +144,6 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); } -#if CONFIG_USE_FAILOVER_IMAGE == 0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -282,4 +272,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } -#endif diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index eeeafda55d..1cc800be09 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -70,16 +70,6 @@ config PCI_64BIT_PREF_MEM default n depends on BOARD_MSI_MS9282 -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_MSI_MS9282 - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_MSI_MS9282 - config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index c595f63b3b..87e20cc3e2 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -42,26 +42,6 @@ config CONFIG_ACPI_SSDTX_NUM default 0x1F depends on BOARD_MSI_MS9652_FAM10 -config USE_FALLBACK_IMAGE - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - -config HAVE_FALLBACK_BOOT - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - -config CONFIG_USE_FAILOVER_IMAGE - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - -config CONFIG_HAVE_FAILOVER_BOOT - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - config GENERATE_PIRQ_TABLE bool default y diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index f99f50b22f..3ab04b0eeb 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -54,7 +54,6 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" @@ -68,14 +67,10 @@ static void post_code(u8 value) { #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -143,8 +138,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_10xxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -163,7 +156,6 @@ static void sio_setup(void) pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -323,5 +315,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x43); // Should never see this post code. } - -#endif -- cgit v1.2.3