From 23836e2345282151b0b46de6cdcd2bb2faee87f6 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 15 Apr 2010 12:39:29 +0000 Subject: zero warnings days... Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/msi/ms7260/romstage.c | 15 +++++++-------- src/mainboard/msi/ms9185/romstage.c | 14 +------------- src/mainboard/msi/ms9282/romstage.c | 9 ++------- 3 files changed, 10 insertions(+), 28 deletions(-) (limited to 'src/mainboard/msi') diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 25cde26dcb..9f84911b36 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -83,7 +83,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) {} static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -93,10 +92,11 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" + #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -144,16 +144,17 @@ static void sio_setup(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { + // Node 0 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, -#endif }; - struct sys_info *sysinfo = - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + int needs_reset = 0; unsigned bsp_apicid = 0; @@ -252,8 +253,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); - memreset_setup(); - /* Do we need apci timer, tsc...., only debug need it for better output */ /* All AP stopped? */ // init_timer(); /* Need to use TMICT to synconize FID/VID. */ diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 10135a5c50..bd1c4a1189 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -71,9 +71,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" -static void memreset_setup(void) -{ -} static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -104,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" /* msi does not want the default */ @@ -129,7 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -144,12 +137,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, -#endif - }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + @@ -278,8 +268,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 83f894a965..c3702084e5 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -68,9 +68,6 @@ #include #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -103,9 +100,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) //#define K8_4RANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/raminit_f.c" -#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" /* msi does not want the default */ @@ -228,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - memreset_setup(); - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); -- cgit v1.2.3