From 1740230ace3aeede3a7ee5cadd1e17744cda07b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 24 May 2018 00:04:22 +0300 Subject: Remove all AMD K8 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/msi/ms9282/Kconfig | 60 ------- src/mainboard/msi/ms9282/Kconfig.name | 2 - src/mainboard/msi/ms9282/board_info.txt | 4 - src/mainboard/msi/ms9282/cmos.layout | 52 ------ src/mainboard/msi/ms9282/devicetree.cb | 182 -------------------- src/mainboard/msi/ms9282/get_bus_conf.c | 123 ------------- src/mainboard/msi/ms9282/irq_tables.c | 127 -------------- src/mainboard/msi/ms9282/mb_sysconf.h | 29 ---- src/mainboard/msi/ms9282/mptable.c | 126 -------------- src/mainboard/msi/ms9282/resourcemap.c | 294 -------------------------------- src/mainboard/msi/ms9282/romstage.c | 181 -------------------- 11 files changed, 1180 deletions(-) delete mode 100644 src/mainboard/msi/ms9282/Kconfig delete mode 100644 src/mainboard/msi/ms9282/Kconfig.name delete mode 100644 src/mainboard/msi/ms9282/board_info.txt delete mode 100644 src/mainboard/msi/ms9282/cmos.layout delete mode 100644 src/mainboard/msi/ms9282/devicetree.cb delete mode 100644 src/mainboard/msi/ms9282/get_bus_conf.c delete mode 100644 src/mainboard/msi/ms9282/irq_tables.c delete mode 100644 src/mainboard/msi/ms9282/mb_sysconf.h delete mode 100644 src/mainboard/msi/ms9282/mptable.c delete mode 100644 src/mainboard/msi/ms9282/resourcemap.c delete mode 100644 src/mainboard/msi/ms9282/romstage.c (limited to 'src/mainboard/msi/ms9282') diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig deleted file mode 100644 index 9314492074..0000000000 --- a/src/mainboard/msi/ms9282/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -if BOARD_MSI_MS9282 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_SOCKET_F - select DIMM_DDR2 - select DIMM_REGISTERED - select NORTHBRIDGE_AMD_AMDK8 - select SOUTHBRIDGE_NVIDIA_MCP55 - select SUPERIO_WINBOND_W83627EHG - select PARALLEL_CPU_INIT - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_512 - select QRANK_DIMM_SUPPORT - select DRIVERS_I2C_ADM1027 - select DRIVERS_I2C_I2CMUX2 - -config MAINBOARD_DIR - string - default msi/ms9282 - -config DCACHE_RAM_BASE - hex - default 0xcc000 - -config DCACHE_RAM_SIZE - hex - default 0x04000 - -config APIC_ID_OFFSET - hex - default 0x10 - -config MAINBOARD_PART_NUMBER - string - default "MS-9282" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 2 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x20 - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_MSI_MS9282 diff --git a/src/mainboard/msi/ms9282/Kconfig.name b/src/mainboard/msi/ms9282/Kconfig.name deleted file mode 100644 index 260c7de96e..0000000000 --- a/src/mainboard/msi/ms9282/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_MSI_MS9282 - bool "MS-9282 (K9SD Master)" diff --git a/src/mainboard/msi/ms9282/board_info.txt b/src/mainboard/msi/ms9282/board_info.txt deleted file mode 100644 index 01c035f93a..0000000000 --- a/src/mainboard/msi/ms9282/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Board name: K9SD Master (MS-9282) -Category: server -Board URL: http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 -Release year: 2006 diff --git a/src/mainboard/msi/ms9282/cmos.layout b/src/mainboard/msi/ms9282/cmos.layout deleted file mode 100644 index c4c90f697f..0000000000 --- a/src/mainboard/msi/ms9282/cmos.layout +++ /dev/null @@ -1,52 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - -checksums - -checksum 392 983 984 diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb deleted file mode 100644 index 747347e504..0000000000 --- a/src/mainboard/msi/ms9282/devicetree.cb +++ /dev/null @@ -1,182 +0,0 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1462 0x9282 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off end # WDTO#, PLED - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux - device i2c 70 on # 0 pca9554 1 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 57 on end - end - end - device i2c 70 on # 0 pca9554 2 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 57 on end - end - end - end - end - device pci 1.1 on # SM 1 - chip drivers/i2c/i2cmux2 # pca9554 SMBus mux - device i2c 72 on # PCA9554 channel 1 - chip drivers/i2c/adm1027 # HWM ADT7476 1 - device i2c 2e on end - end - end - device i2c 72 on # PCA9545 channel 2 - chip drivers/i2c/adm1027 # HWM ADT7463 - device i2c 2e on end - end - end - device i2c 72 on end # PCA9545 channel 3 - device i2c 72 on # PCA9545 channel 4 - chip drivers/i2c/adm1027 # HWM ADT7476 2 - device i2c 2e on end - end - end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # P2P - device pci 4.0 on end - end - device pci 7.0 on end # reserve - device pci 8.0 on end # MAC0 - device pci 9.0 on end # MAC1 - device pci a.0 on - device pci 0.0 on - device pci 4.0 on end # PCI-E LAN1 - device pci 4.1 on end # PCI-E LAN2 - end - end # 0x376 - device pci b.0 on end # PCI E 0x374 - device pci c.0 on end - device pci d.0 on # SAS - device pci 0.0 on end - end # PCI E 1 0x378 - device pci e.0 on end # PCI E 0 0x375 - device pci f.0 on end # PCI E 0x377, PCI-E slot - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c deleted file mode 100644 index a072d6aa36..0000000000 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * Copyright (C) 2006 MSI - * Written by Bingxun Shi for MSI. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include "mb_sysconf.h" - -// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -struct mb_sysconf_t mb_sysconf; - -unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, - 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 -}; - -unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, - 0x20202020, - 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -}; - -static unsigned get_bus_conf_done = 0; - -void get_bus_conf(void) -{ - - unsigned apicid_base; - struct mb_sysconf_t *m; - - struct device *dev; - int i; - - if (get_bus_conf_done == 1) - return; //do it only once - - get_bus_conf_done = 1; - - sysconf.mb = &mb_sysconf; - - m = sysconf.mb; - memset(m, 0, sizeof(struct mb_sysconf_t)); - - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for (i = 0; i < sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } - - get_sblk_pci1234(); - - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain - - m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - - /* MCP55 */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06, 0)); - if (dev) { - m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sysconf.sbdn + 0x06); - } - - for (i = 2; i < 8; i++) { - dev = - dev_find_slot(m->bus_mcp55[0], - PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); - if (dev) { - m->bus_mcp55[i] = - pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); - } - } - -/*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) - apicid_base = get_apicid_base(1); - else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; - m->apicid_mcp55 = apicid_base + 0; - -} diff --git a/src/mainboard/msi/ms9282/irq_tables.c b/src/mainboard/msi/ms9282/irq_tables.c deleted file mode 100644 index cbb621a906..0000000000 --- a/src/mainboard/msi/ms9282/irq_tables.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * Copyright (C) 2006 MSI - * Written by Bingxun Shi for MSI. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include -#include "mb_sysconf.h" - -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - struct mb_sysconf_t *m; - unsigned sbdn; - - uint8_t sum = 0; - int i; - - get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - sbdn = sysconf.sbdn; - m = sysconf.mb; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (uint8_t *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = m->bus_mcp55[0]; - pirq->rtr_devfn = ((sbdn + 6) << 3) | 0; - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x0370; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; -//pci bridge - write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1, - 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - - for (i = 1; i < sysconf.hc_possible_num; i++) { - if (!(sysconf.pci1234[i] & 0x1)) - continue; - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; - - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, - 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - slot_num++; - } - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "done.\n"); - - return (unsigned long)pirq_info; - -} diff --git a/src/mainboard/msi/ms9282/mb_sysconf.h b/src/mainboard/msi/ms9282/mb_sysconf.h deleted file mode 100644 index 3edba64696..0000000000 --- a/src/mainboard/msi/ms9282/mb_sysconf.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * Copyright (C) 2006 MSI - * Written by Bingxun Shi for MSI. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MB_SYSCONF_H - -#define MB_SYSCONF_H - -struct mb_sysconf_t { - unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; -}; - -#endif diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c deleted file mode 100644 index d3a4287b96..0000000000 --- a/src/mainboard/msi/ms9282/mptable.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * Copyright (C) 2006 MSI - * Written by Bingxun Shi for MSI. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "mb_sysconf.h" - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - struct mb_sysconf_t *m; - unsigned sbdn; - - int i, j, bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - get_bus_conf(); - sbdn = sysconf.sbdn; - m = sysconf.mb; - - mptable_write_buses(mc, NULL, &bus_isa); - -/*I/O APICs: APIC ID Version State Address*/ - { - struct device *dev; - struct resource *res; - uint32_t dword; - - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, m->apicid_mcp55, 0x11, - res2mmio(res, 0, 0)); - } - - dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0xd00002d2; - pci_write_config32(dev, 0x84, dword); - - } - - - } - - mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); - -//SMBUS - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); - -//USB1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 - -//USB2.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 - -//SATA1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 - -//SATA2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 - -//SATA3 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 - -//NIC1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 -//NIC2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - - for (j = 7; j >= 2; j--) { - if (!m->bus_mcp55[j]) - continue; - for (i = 0; i < 4; i++) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } - - for (j = 0; j < 1; j++) - for (i = 0; i < 4; i++) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/msi/ms9282/resourcemap.c b/src/mainboard/msi/ms9282/resourcemap.c deleted file mode 100644 index 53b470a5e4..0000000000 --- a/src/mainboard/msi/ms9282/resourcemap.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Stefan Reinauer - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * Copyright (C) 2006 MSI - * Written by Bingxun Shi for MSI. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * MSI ms9282 needs a different resource map - * - */ - -static void setup_ms9282_resource_map(void) -{ - static const unsigned int register_values[] = { -#if 1 - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, -#endif -#if 1 - - /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, - - /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, -#endif -#if 1 - - /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, - - /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, -#endif - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ -#if 1 -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, -#endif - - }; - - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); -} diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c deleted file mode 100644 index 6bde880622..0000000000 --- a/src/mainboard/msi/ms9282/romstage.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 AMD - * Written by Yinghai Lu for AMD. - * - * Copyright (C) 2006 MSI - * Written by Bingxun Shi for MSI. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include "northbridge/amd/amdk8/setup_resource_map.c" -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) - -unsigned get_sbdn(unsigned bus); - -unsigned get_sbdn(unsigned bus) -{ - pci_devfn_t dev; - - /* Find the device. */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); - - return (dev >> 15) & 0x1f; -} - -void memreset(int controllers, const struct mem_controller *ctrl) { } - -void activate_spd_rom(const struct mem_controller *ctrl) -{ -#define SMBUS_SWITCH1 0x70 -#define SMBUS_SWITCH2 0x72 - unsigned device=(ctrl->channel0[0])>>8; - smbus_send_byte(SMBUS_SWITCH1, device); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); -} - -int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "lib/generic_sdram.c" -#include "resourcemap.c" -#include "cpu/amd/dualcore/dualcore.c" -#include - -//set GPIO to input mode -#define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ - -#include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" - -/* FIXME - * Dummy method to allow build - * Determine if this board / CPU should support - * FID/VID and implement proper support if so - */ -#if IS_ENABLED(CONFIG_SET_FIDVID) -void init_fidvid_ap(u32 bsp_apicid, u32 apicid) { } -#endif - -static void sio_setup(void) -{ - uint32_t dword; - uint8_t byte; - - byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); -} - -//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. -#define RC0 (2 << 8) -#define RC1 (1 << 8) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - static const uint16_t spd_addr[] = { - // Node 0 - RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, - RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, - // node 1 - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, - }; - - unsigned bsp_apicid = 0; - int needs_reset; - struct sys_info *sysinfo = &sysinfo_car; - - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - } - - if (bist == 0) { - //init_cpus(cpu_init_detectedx); - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - setup_ms9282_resource_map(); - - setup_coherent_ht_domain(); - - wait_all_core0_started(); - -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) - // It is said that we should start core1 after all core0 launched - start_other_cores(); - //wait_all_other_cores_started(bsp_apicid); -#endif - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - - init_timer(); /* Need to use TMICT to synchronize FID/VID. */ - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= mcp55_early_setup_x(); - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } - - //It's the time to set ctrl now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - - enable_smbus(); - - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); -} -- cgit v1.2.3