From 84101434c0aae2562bab0231877f166a58ab2b95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 13 Feb 2024 15:59:51 +0100 Subject: mb/msi/ms7d25,ms7e06: Enable discrete TPM module support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that multiple TPM drivers may be compiled in, it is possible to support switching between fTPM and dTPM. The patch adds: - Device tree entry for PC80 discrete TPM - TPM PIRQ# GPIO active low routed to IOAPIC for TPM interrupt - MEMORY_MAPPED_TPM option to board's Kconfig to enable PC80 TPM driver When the ME is disabled, e.g. via HECI command, chipset will route the TPM traffic to SPI automatically. When a SPI TPM is connected to the JTPM1 on the board, it will be probed successfully and initialized in place of inactive PTT/fTPM. Change-Id: Ie6e7026b6f1cec842bce4ef40b6db7feb75200e3 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/80456 Reviewed-by: Maciej Pijanowski Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/msi/ms7e06/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/msi/ms7e06/gpio.h') diff --git a/src/mainboard/msi/ms7e06/gpio.h b/src/mainboard/msi/ms7e06/gpio.h index 413ada8ef3..71b30e0c8c 100644 --- a/src/mainboard/msi/ms7e06/gpio.h +++ b/src/mainboard/msi/ms7e06/gpio.h @@ -536,8 +536,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI), /* GPP_E6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI), - /* GPP_E7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), + /* GPP_E7 - TPM_PIRQ# */ + PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), /* GPP_E8 - SATALED# */ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), /* GPP_E9 - USB_OC0# */ -- cgit v1.2.3