From a688b7cb7ba4fe1d5040da11899a0275a420ff17 Mon Sep 17 00:00:00 2001
From: Renze Nicolai <renze@rnplus.nl>
Date: Fri, 18 Nov 2016 23:08:13 +0100
Subject: mainboard/ms7721: Copy files from "asus/f2a85-m" to "msi/ms7721".
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This patch adds a copy of the Asus F2A85-M code with only minimal changes.
(to ensure that the code compiles)

A second commit will be published to remove the copied code parts that
don't apply to the MS-7221 and to make everything else actually work
on the MS-7221 board.

Change-Id: I1426c0876c7bfeb264231c0d338301133c721484
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/17494
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/mainboard/msi/ms7721/dsdt.asl | 106 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 src/mainboard/msi/ms7721/dsdt.asl

(limited to 'src/mainboard/msi/ms7721/dsdt.asl')

diff --git a/src/mainboard/msi/ms7721/dsdt.asl b/src/mainboard/msi/ms7721/dsdt.asl
new file mode 100644
index 0000000000..0028855c94
--- /dev/null
+++ b/src/mainboard/msi/ms7721/dsdt.asl
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",		/* Output filename */
+	"DSDT",			/* Signature */
+	0x02,			/* DSDT Revision, needs to be 2 for 64bit */
+	"ASUS  ",		/* OEMID */
+	"COREBOOT",		/* TABLE ID */
+	0x00010001		/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
+
+	/* Globals for the platform */
+	#include "acpi/mainboard.asl"
+
+	/* PCI IRQ mapping for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+	/* Describe the processor tree (\_PR) */
+	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+	/* Describe the supported Sleep States for this Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
+
+	/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+	#include "acpi/sleep.asl"
+
+	Scope(\_SB) {
+		/* global utility methods expected within the \_SB scope */
+		#include <arch/x86/acpi/globutil.asl>
+
+		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+		#include "acpi/routing.asl"
+
+		Device(PWRB) {
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})
+			Name(_STA, 0x0B)
+		}
+
+		Device(PCI0) {
+			/* Describe the AMD Northbridge */
+			#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+			/* Describe the AMD Fusion Controller Hub Southbridge */
+			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+			/**
+			 * TODO: The devices listed here (SBR0 and SBR1) do not appear to
+			 *       be referenced anywhere and could possibly be removed.
+			 */
+			Device(SBR0) { /* PCIe 1x SB */
+				Name(_ADR, 0x00150000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(ABR0) }   /* APIC mode */
+					Return (PBR0)              /* PIC mode  */
+				}
+			}
+
+			Device(SBR1) { /* Onboard network */
+				Name(_ADR, 0x00150001)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT, 0) {
+					If(PMOD){ Return(ABR1) }   /* APIC mode */
+					Return (PBR1)              /* PIC mode  */
+				}
+			}
+		}
+
+		/* Describe PCI INT[A-H] for the Southbridge */
+		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+	}   /* End Scope(_SB)  */
+
+	/* Describe SMBUS for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+	/* Define the General Purpose Events for the platform */
+	#include "acpi/gpe.asl"
+
+	/* Define the Thermal zones and methods for the platform */
+	#include "acpi/thermal.asl"
+
+	/* Define the System Indicators for the platform */
+	#include "acpi/si.asl"
+
+}
+/* End of ASL file */
-- 
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