From b4f47e8067a7ef55ad5e2f18058031a871edbfef Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 11 Nov 2023 17:25:48 -0500 Subject: nb/intel/haswell: Move SPD addresses to devicetree Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy. Patch also covers recently added Z97 boards using Broadwell MRC. Also update util/autoport to match. abuild passes for all affected boards. autoport builds, but otherwise untested. Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/msi/h81m-p33/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/msi/h81m-p33/devicetree.cb') diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb index f72ed9ff1b..6051ca66fa 100644 --- a/src/mainboard/msi/h81m-p33/devicetree.cb +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -2,6 +2,7 @@ chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end -- cgit v1.2.3