From c5f1dc96bf0b18245d7986463ae56958c44d24f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 10 Apr 2021 22:51:15 +0200 Subject: mb/*: drop LPC generic range for port 80 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/libretrend/lt1000/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/libretrend') diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9fedde5db8..5e5c9beddf 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -28,7 +28,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff - register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f # Disable DPTF register "dptf_enable" = "0" -- cgit v1.2.3