From 9c1c00968c943659bab2a817892e5a9be9dfb7c0 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 29 Jul 2020 20:48:08 +0200 Subject: soc/intel/skylake: Enable thermal subsystem depending on devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/libretrend/lt1000/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/libretrend') diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index a58e169b8c..a355ee4169 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -54,7 +54,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms @@ -174,6 +173,7 @@ chip soc/intel/skylake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem -- cgit v1.2.3