From b30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 15 Jul 2019 18:04:23 +0200 Subject: sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/mainboard/lenovo/l520/devicetree.cb | 1 - src/mainboard/lenovo/s230u/devicetree.cb | 1 - src/mainboard/lenovo/t420/devicetree.cb | 1 - src/mainboard/lenovo/t420s/devicetree.cb | 1 - src/mainboard/lenovo/t430/devicetree.cb | 1 - src/mainboard/lenovo/t430s/devicetree.cb | 1 - src/mainboard/lenovo/t520/variants/t520/devicetree.cb | 1 - src/mainboard/lenovo/t520/variants/w520/devicetree.cb | 1 - src/mainboard/lenovo/t530/variants/t530/devicetree.cb | 1 - src/mainboard/lenovo/t530/variants/w530/devicetree.cb | 1 - src/mainboard/lenovo/x131e/devicetree.cb | 1 - src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb | 1 - src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/lenovo/x220/devicetree.cb | 1 - src/mainboard/lenovo/x230/devicetree.cb | 1 - 15 files changed, 15 deletions(-) (limited to 'src/mainboard/lenovo') diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 48c2ea010e..024b8f8dd1 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -46,7 +46,6 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x00000000" register "gpi13_routing" = "2" register "gpi6_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index a9e8babe6e..15d323d8b9 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi7_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index c4092fe901..6deff6039c 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index d1e3f75499..aa6cc68154 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 2731b69ec0..f7e04367c6 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 21d54acf11..0c2f668897 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index eff2d69304..7893daf9ec 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index ceca46ea84..8716046410 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 335543a8f7..190539ac1f 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 0a80fa1d8c..0844124f0e 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" register "gen4_dec" = "0x000c06a1" - register "p_cnt_throttling_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 21d38f5ab2..2a98a60cac 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "0x0065" - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 8caa0d1a2f..288870f81d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -70,7 +70,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6ece08bee6..bf74d710bb 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/intel/nehalem register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "p_cnt_throttling_supported" = "1" register "c2_latency" = "1" register "docking_supported" = "1" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 360de04943..26fa1a4d1f 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -69,7 +69,6 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 4687e9ccc3..61a5468a78 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -72,7 +72,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported - register "p_cnt_throttling_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" -- cgit v1.2.3