From 77757c22b9eede92234d07d65a23fdf4b970c8cf Mon Sep 17 00:00:00 2001
From: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date: Sun, 4 Jan 2015 21:33:39 +1100
Subject: mainboard/*/romstage.c: Sanitize system header inclusions

Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.

Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
 src/mainboard/lenovo/t530/romstage.c | 4 ++--
 src/mainboard/lenovo/t60/romstage.c  | 6 +++---
 src/mainboard/lenovo/x201/romstage.c | 8 ++++----
 src/mainboard/lenovo/x220/romstage.c | 8 ++++----
 src/mainboard/lenovo/x230/romstage.c | 8 ++++----
 src/mainboard/lenovo/x60/romstage.c  | 6 +++---
 6 files changed, 20 insertions(+), 20 deletions(-)

(limited to 'src/mainboard/lenovo')

diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 0a49ed05c3..fbf47ac9ca 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -24,8 +24,8 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/raminit_native.h"
-#include "southbridge/intel/bd82x6x/pch.h"
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
 
 void pch_enable_lpc(void)
 {
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 571a21cfd6..094e1dc105 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -36,9 +36,9 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <halt.h>
-#include "northbridge/intel/i945/i945.h"
-#include "northbridge/intel/i945/raminit.h"
-#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
 #include "dock.h"
 
 void setup_ich7_gpios(void)
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index be49067736..64011b1f6e 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -42,11 +42,11 @@
 #include "gpio.h"
 #include "dock.h"
 #include "arch/early_variables.h"
-#include "southbridge/intel/ibexpeak/pch.h"
-#include "northbridge/intel/nehalem/nehalem.h"
+#include <southbridge/intel/ibexpeak/pch.h>
+#include <northbridge/intel/nehalem/nehalem.h>
 
-#include "northbridge/intel/nehalem/raminit.h"
-#include "southbridge/intel/ibexpeak/me.h"
+#include <northbridge/intel/nehalem/raminit.h>
+#include <southbridge/intel/ibexpeak/me.h>
 
 static void pch_enable_lpc(void)
 {
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index d9c8aa04e1..d0fb8e6abc 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -30,10 +30,10 @@
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit_native.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 0bb137e732..4ea272d381 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -32,10 +32,10 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit_native.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cbfs.h>
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index af9b1be653..b9976377b2 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -36,9 +36,9 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <halt.h>
-#include "northbridge/intel/i945/i945.h"
-#include "northbridge/intel/i945/raminit.h"
-#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
 #include "dock.h"
 
 void setup_ich7_gpios(void)
-- 
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