From 4513020064cc4765e723f6f3cc2b8a45a0dc6545 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 4 Jan 2019 14:23:54 +0100
Subject: cpu/intel: Use the common code to initialize the romstage timestamps
MIME-Version: 1.0
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The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/mainboard/lenovo/t400/romstage.c            | 4 ----
 src/mainboard/lenovo/t60/romstage.c             | 5 -----
 src/mainboard/lenovo/thinkcentre_a58/romstage.c | 3 ---
 src/mainboard/lenovo/x200/romstage.c            | 5 -----
 src/mainboard/lenovo/x60/romstage.c             | 5 -----
 src/mainboard/lenovo/z61t/romstage.c            | 5 -----
 6 files changed, 27 deletions(-)

(limited to 'src/mainboard/lenovo')

diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 6d93112588..1a708ae195 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -30,7 +30,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
-#include <timestamp.h>
 #include "dock.h"
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -68,9 +67,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int err;
 	u16 reg16;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 44ac585721..9216848f06 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -168,10 +167,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int dock_err;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index 6d0bc97f10..31de0e3e9d 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -68,9 +68,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich7_enable_lpc();
 	mb_lpc_setup();
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 2cd1b213b0..a0a1ace16e 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -29,12 +29,10 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
-#include <timestamp.h>
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define MCH_DEV PCI_DEV(0, 0, 0)
 
-
 static void early_lpc_setup(void)
 {
 	/* Set up SuperIO LPC forwards */
@@ -56,9 +54,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 9c5930ebb1..7b75d16444 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -166,10 +165,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int s3resume = 0;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index ed0cc7606a..985cebaa87 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -168,10 +167,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int dock_err;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
-- 
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