From 3b452e0a797b54a05b97725f4e4e320c51098754 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 3 Oct 2019 09:16:10 +0200 Subject: nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/x201/romstage.c | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'src/mainboard/lenovo') diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1440c19573..81752e88ae 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -26,28 +26,6 @@ void mainboard_lpc_init(void) { - /* EC Decode Range Port60/64, Port62/66 */ - /* Enable EC, PS/2 Keyboard/Mouse */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN | GAMEL_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); - - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); - /* Enable USB Power. We need to do it early for usbdebug to work. */ ec_set_bit(0x3b, 4); } -- cgit v1.2.3