From dc584c3f221bb59ee6b89e5517617b9d1d74bcf3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 20:37:21 +0100 Subject: nb/intel/i945: Move boilerplate romstage to a common location This adds callbacks for mainboard specific init. Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x60/romstage.c | 100 +++++++++--------------------------- 1 file changed, 25 insertions(+), 75 deletions(-) (limited to 'src/mainboard/lenovo/x60') diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 6eeb2d12ba..d230aa3c57 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -15,26 +15,18 @@ * GNU General Public License for more details. */ -#include -#include #include +#include +#include #include #include -#include -#include -#include -#include -#include -#include #include -#include #include #include -#include #include "dock.h" /* Override the default lpc decode ranges */ -static void mb_lpc_decode(void) +void mainboard_lpc_decode(void) { // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); @@ -56,7 +48,24 @@ static void early_superio_config(void) pnp_set_enable(dev, 1); } -static void rcba_config(void) +void mainboard_superio_config(void) +{ + /* Set up GPIO's early since it is needed for dock init */ + i82801gx_setup_bars(); + setup_pch_gpios(&mainboard_gpio_map); + + dlpc_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (dock_present()) { + dock_connect(); + early_superio_config(); + } +} + +void mainboard_late_rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; @@ -87,68 +96,9 @@ static void rcba_config(void) RCBA64(IOTR3) = 0x000200f0000c0801ULL; } -void mainboard_romstage_entry(void) -{ - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; - - enable_lapic(); - - /* Set up GPIO's early since it is needed for dock init */ - i82801gx_setup_bars(); - setup_pch_gpios(&mainboard_gpio_map); - i82801gx_lpc_setup(); - mb_lpc_decode(); - - dlpc_init(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Set up the console */ - console_init(); - - if (dock_present()) - printk(BIOS_DEBUG, "Dock is present\n"); - else - printk(BIOS_DEBUG, "Dock is not present\n"); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - system_reset(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i82801gx_early_init(); - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); +void mainboard_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x51; } -- cgit v1.2.3