From ac1b6def75e8dd3cd792a55d85451fa6b43e472e Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sat, 31 Jan 2015 17:46:29 +0100 Subject: lenovo/x230: Set xhci_switchable_ports and superspeed_capable_ports. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes USB3 ports degraded to USB2 speeds. Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/8313 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x230/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/lenovo/x230/devicetree.cb') diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 5130410e90..3a05b5a89a 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -67,6 +67,9 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported -- cgit v1.2.3