From 6b95507ec5b087658178a325bdc68570bc48bb20 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Fri, 8 May 2020 16:40:48 +0800 Subject: mainboard/lenovo/x230: Add ThinkPad x230s as a variant The code is based on autoport and that for X230. Major differences are: - Only one DDR3 slot - HM77 PCH - M.2 socket instead of mini pci-e - no docking - no tpm Tested: - CPU i5-3337U - Slotted DIMM 8GiB - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.9 within Debian GNU/Linux stable, loaded from Seabios. Untested: - Touch screen, which is said to work under ubuntu but not debian. Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/mainboard/lenovo/x230/devicetree.cb | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'src/mainboard/lenovo/x230/devicetree.cb') diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index e34734c4c3..52a4cd3e47 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -60,7 +60,8 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "xhci_switchable_ports" = "0xf" + # Wire port 4 (wwan usb) to ehci for it lacks superspeed components + register "xhci_switchable_ports" = "0x7" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" @@ -89,9 +90,7 @@ chip northbridge/intel/sandybridge end end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #3 (expresscard) + device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 @@ -136,7 +135,6 @@ chip northbridge/intel/sandybridge register "event7_enable" = "0x01" register "event8_enable" = "0x7b" register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" register "eventb_enable" = "0x00" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" -- cgit v1.2.3