From e2ce52f59f55791ac3e50457e221931a44929180 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 7 Oct 2023 08:03:30 +0200 Subject: mb/lenovo/x220: Update devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Disable unconnected PCH PCIe ports 1 + 3. - Add smbios_slot_desc to WLAN PCIe port - Add comment for PCIe port 7 that might have a XHCI controller connected (some variants only). Test: Lenovo X220 still boots and all devices are still working fine. The WLAN slot is shown in dmidecode -t 9. Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/78291 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan Reviewed-by: Kyösti Mälkki --- src/mainboard/lenovo/x220/devicetree.cb | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'src/mainboard/lenovo/x220') diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index b6736d2412..866d6c3b41 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -77,9 +77,12 @@ chip northbridge/intel/sandybridge end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 device ref hda on end # High Definition Audio - device ref pcie_rp1 on end # PCIe Port #1 - device ref pcie_rp2 on end # PCIe Port #2 (wlan) - device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 on # PCIe Port #2 (wlan) + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort" + "WIFI" "SlotDataBusWidth1X" + end + device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 @@ -91,7 +94,7 @@ chip northbridge/intel/sandybridge end end # PCIe Port #5 (SD) device ref pcie_rp6 off end # PCIe Port #6 - device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp7 on end # PCIe Port #7 Optional XHCI controller device ref pcie_rp8 off end # PCIe Port #8 device ref ehci1 on end # USB2 EHCI #1 device ref pci_bridge off end # PCI bridge -- cgit v1.2.3