From 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 22 Jul 2023 12:49:05 -0400 Subject: mb/*: Update SPD mapping for sandybridge boards Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) Reviewed-by: Martin L Roth --- src/mainboard/lenovo/x220/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/lenovo/x220/devicetree.cb') diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 049eea6d84..b6736d2412 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" register "ec_present" = "1" # I have an embedded controller register "max_mem_clock_mhz" = "666" # So DDR3 freq = 1333 -- cgit v1.2.3