From 1b7609c0e88ba820dbc2251fad0d994e2b54a154 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 25 Jun 2016 11:40:00 +0300 Subject: intel/nehalem: Use romstage_handoff for S3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/lenovo/x201/romstage.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'src/mainboard/lenovo/x201/romstage.c') diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2bfa19c412..107cc46fc8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -277,20 +278,13 @@ void mainboard_romstage_entry(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume) { - acpi_prepare_for_resume(); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + romstage_handoff_init(s3resume); + + if (s3resume) + acpi_prepare_for_resume(); + else quick_ram_check(); - } -#endif #if CONFIG_LPC_TPM init_tpm(s3resume); -- cgit v1.2.3