From 823020d56be1bf6425b4e433a1f1c2bbc2c4c90b Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 22 Jul 2016 22:53:19 +0300 Subject: intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With this change, CBMEM region is set early-on as WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/lenovo/x200/romstage.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/lenovo/x200/romstage.c') diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index c1e193a973..8c97ae1554 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -162,7 +162,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); -- cgit v1.2.3