From 96ae7a3a2d38b96c1dfee57fda2c2eaab7e9e762 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Wed, 16 Oct 2019 23:22:10 +0800 Subject: mb/lenovo/x200: Add ThinkPad X301 as a variant It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/x200/devicetree.cb | 28 +--------------------------- 1 file changed, 1 insertion(+), 27 deletions(-) (limited to 'src/mainboard/lenovo/x200/devicetree.cb') diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 4efcc255ec..fdd69ec91e 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -73,12 +73,6 @@ chip northbridge/intel/gm45 # Set thermal throttling to 75%. register "throttle_duty" = "THTL_75_0" - # Enable PCIe ports 1,2,4 as slots (Mini * PCIe). - register "pcie_slot_implemented" = "0xb" - # Set power limits to 10 * 10^0 watts. - # Maybe we should set less for Mini PCIe. - register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" register "gen3_dec" = "0x001c1681" @@ -114,10 +108,7 @@ chip northbridge/intel/gm45 device pci 1c.2 on subsystemid 0x17aa 0x20f3 # UWB end # PCIe Port #3 - device pci 1c.3 on - subsystemid 0x17aa 0x20f3 # Expresscard - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 + # PCIe Port #4 is configured in override tree. device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI @@ -154,7 +145,6 @@ chip northbridge/intel/gm45 device pnp ff.1 on # dummy end register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" end chip ec/lenovo/h8 @@ -192,22 +182,6 @@ chip northbridge/intel/gm45 register "bdc_gpio_num" = "7" register "bdc_gpio_lvl" = "0" end - - chip superio/nsc/pc87382 - device pnp 164e.3 on # Digitizer - io 0x60 = 0x200 - irq 0x29 = 0xb0 - irq 0x70 = 0x5 - irq 0xf0 = 0x82 - end - # IR, not connected - device pnp 164e.2 off end - # GPIO, not connected - device pnp 164e.7 off end - # DLPC, not connected - device pnp 164e.19 off end - end - end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 -- cgit v1.2.3